Re: XF86 Config pour SiS 6205 ?

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著者: Tim Walker
日付:  
To: guilde
題目: Re: XF86 Config pour SiS 6205 ?
romuald jouffrey wrote:
>
> Désolé, mais je ne sais pas comment t'aider pour ton pb, par contre,
> tu dis :
> >la video utilise de la ram principal, pas de la ram dedie. (C'est plus vite comme ca, selon
> >la doc!)
>
> NON nOn, c'est pas plus rapide comme ca, mais c'est moins cher à
> fabriquer car pas de ram sur la carte vidéo (vu qu'il n'y a pas de carte
> vidéo :-))) Le bus est occupé par les flux vidéo en plus, donc c'est
> forcément moins rapide ...
>
> Faut pas croire tout ce qu'on raconte dans les docs :-)


Je suis le dernier a crois tout ce qu'on me raconte dans les docs,
mais les docs disent le suivent:

".....

No dedicated video memory exists. Instead, the computer is built around
a
unified memory architecture (UMA). The shared frame buffer (SFB) is
located in a
reserved portion of the main memory, with the remainder of the main
memory
available for conventional system memory.

The SiS 6205 graphics controller requests memory accesses from the SiS
5511
memory controller. These requests are granted as soon as any
outstanding request
s for the system memory have completed. This arbitration is conducted
on three
signal lines: VGAREQ#, VGAGNT# and PREQ (if the high/low priority scheme
is enabled).

Since the main memory is not dual ported, the display refresh and data
input
cannot be conducted simultaneously. Instead, display refresh is given
priority,
and data access is queued to take place when it can. Thus the video
data
bandwidth on the memory bus limits the performance when the computer is
used without
level-two (L2) cache memory. When a cache memory module is installed,
however,
the processor can read or write data to the L2 cache memory, and process
it,
without needing to compete with the graphics controller for access to
the main memory.

One advantage that UMA has, over computers that have separate video
memory, is
that blocks of graphics data can be transferred between the main memory
and
video memory via the 66 MHz, 64-bit Processor-Local bus, instead of
having to go
via the 33 MHz, 32-bit PCI bus: a four-fold increase in bandwidth.

...."

alors peut-etre c'est moins vite - peut-etre c'est plus vite !!! ;)

-- 
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Tim Walker                                             Hewlett-Packard
Tel:     (+33) 04.76.14.12.33          Telecom Infrastructure Division
Fax:     (+33) 04.76.14.14.88            38053 Grenoble Cedex 9 FRANCE


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